C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits. (arXiv:2301.10216v1 [cs.LO])

Since the development of semiconductor technologies, exascale computing and
its associated applications have required increasing degrees of efficiency.
Semiconductor-transistor-based circuits (STbCs) have struggled in increasing
the GHz frequency. Emerging as an alternative to STbC, the superconducting
electrons (SCE) technology promises higher-speed clock frequencies at ultra-low
power consumption. The rapid single flux quantum (RSFQ) circuits have a
theoretical potential for three orders of magnitude reduction in power while
operating at clock frequencies higher than 100 GHz. Although the security in
semiconductor technology has been extensively researched and developed, the
security design in the superconducting field requires field demands attention.
In this paper, C-SAR is presented that aims to protect the superconducting
circuit electronics from Boolean satisfiability (SAT) based attacks. The SAT
attack is an attack that can break all the existing combinational logic locking
techniques. C-SAR can immunize against SAT attacks by increasing the key search
space and prolonging the clock cycles of attack inputs. Even in the worst case
of C-SAR, in face of S-SAT a specially designed SAT attack, C-SAR can also soar
the attack cost exponentially with key bits first, then linearly with the
length of camouflaged DFF array. We have shown in this work that the cost of
C-SAR is manageable as it only linearly increases as a function of key bits.